1. Field of Use
The present invention relates to cache memory systems and more particularly to cache memory systems shared by a plurality of processing units.
2. Background
The related copending patent application titled, "Multiprocessor Shared Pipeline Cache Memory", discloses a cache memory subsystem which has two pipeline stages shareable by a plurality of sources including a number of independently operated central processing units. The first pipeline stage provides for a directory search and compare operation while the second pipeline stage performs the operations of fetching the requested data from the cache buffer memory and its transfer to the requesting source. Timing and control apparatus couples to the sources and allocates each processing unit, time slots which offset their operations by a pipeline stage. Thus, the processing units operate independently and conflict free.
In sharing a cache memory or main memory between a plurality of processing units, there can occur sequences of events or operations which can give rise to incoherency. To avoid this, one solution is to have the processing units share the available memory space and provide a locking mechanism which would prevent one processing unit from modifying information being accessed by another processing unit. While this solution works well for main memory, it can result in excessive data replacement or thrashing which reduces the cache hit ratio. Additionally, this type of arrangement reduces the ability for each processing unit to operate independently.
To avoid this problem, the related copending patent application titled, "A Coherent Cache System Shared by a Pair of Processing Units" discloses an arrangement which permits for completely independent operation of each processing unit by allocating one-half of the total available cache memory space by separate accounting replacement apparatus included within the buffer memory stage. During each directory allocation cycle performed for a processing unit, the allocated space of the other processing unit is checked for the presence of a multiple allocation. The address of the multiple allocated location associated with the processing unit assigned the lower priority is stored in a multiple allocation memory allowing earliest data replacement thereby maintaining data coherency between independently operated processing units.
While the above arrangement prevents data incoherency between independently operated processing units, incoherency still can arise in tightly coupled processing systems in which processing or data handling units share a common main memory. To maintain coherency in such systems, each processing unit which has an associated cache includes a listener device which monitors memory writes applied by other units to a common system bus. This enables the processing unit to update the contents of its cache to reflect changes in the corresponding main memory data made by other units ensuring cache coherency. Sometimes during the updating process, conditions can occur which make it impossible for a processing unit to update cache accurately. For example, the data received by the listener device could be garbled or the memory write applied to the bus produced a time out. The latter condition may occur if the system includes resiliency features such as those disclosed in the copending patent application of George J. Barlow and James W. Keeley entitled, "Resilient Bus System", bearing Ser. No. 06/623,264, filed on June 21, 1984 and now U.S. Pat. No. 4,763,243 and assigned to the same assignee as named herein.
Normally, in the case of garbled data, an error condition would be detected and the data would be discarded. In those cases where the garbled data was presented to the cache unit, the resulting hit or miss generated would not produce trustworthy indications. For example, a miss if wrong could produce multiple allocations. A hit if wrong could result in the updating of the wrong processing unit's data. At this point, whatever action is taken at this point makes the cache unit's contents incoherent.
The above is also true for memory write issued by each processing unit. That is, if the memory write applied to the system bus by the processing unit produces an error, inhibiting the contents of its own cache unit from being updated by that write would prevent further damage. However, it also gives rise to a potential incoherency. To overcome the above, a possible solution would be to provide additional error detection and correction capabilities throughout the system which would be able to reconstruct the bad or garbled data. However, this would prove expensive and quite time-consuming thereby causing a substantial decrease in cache performance. Moreover, it still may not be possible to ensure coherency under all conditions particularly within a system which includes resiliency features.
Accordingly, it is a primary object of the present invention to provide a technique and apparatus which is able to maintain cache coherency in a highly reliable fashion without sacrificing overall performance.
It is a further object of the present invention to maintain coherency within a tightly coupled resilient data processing system.